1. Field of the Invention
The present invention relates to a circuit and method for sensing a memory cell, and in particular, to a circuit and method for sensing a memory cell having a plurality of threshold voltages.
2. Background of the Related Art
As shown in FIG. 1, a related art sensing circuit for reading a multiple level cell includes a PMOS load transistor PM11, which has a source receiving a power voltage VCC and a gate and a drain connected together. An NMOS transistor NM11 has a drain connected with the drain of the PMOS load transistor PM11. An output signal from the drain of the NMOS transistor NM11 is inverted and is connected with its gate to configure a bit line regulation circuit 1. A bit line selection circuit 2 connects a predetermined cell with the bit line. PMOS transistors PM12 through PM14 have sources that respectively receive the power voltage VCC and gates respectively connected together and with the gate of the PMOS load transistor PM11.
NMOS transistors NM12 through NM14 have sources that are respectively connected with the drains of the PMOS transistors PM12 through PM14. The drains of the NMOS transistors NM12 through NM14 are connected with ground, respectively. NMOS transistors NM15 through NM17 have drains respectively connected with rated current power sources IREF1, IREF2 and IREF3 and sources respectively connected with the ground. Gates and drains of the NMOS transistors NM15 through NM17 are connected together and are respectively connected with the gates of the NMOS transistors NM12 through NM14. Inverters INV12 through INV14 are for inverting the output signals from the respectively connected drains of the PMOS transistors PM12 through PM14 and drains of the NMOS transistors NM12 through NM14. A coding logic circuit 3 receives the output signals from the inverters INV12 through INV14 and inverts the received signals into 2-bit digital signals.
The operation of the related art sensing circuit reading a multiple level cell will now be described. First, the bit line selection circuit 2 connects the memory array including a plurality of memory cells and the drain of a predetermined cell, which is to be read, with the bit line.
In the sensing mode, the bit line regulation circuit 1 constantly maintains the drain voltage of the cell. The PMOS load transistor PM11 and three current comparison type sensor amplifiers connect the bit line current and a current mirror. In addition, the coding logic circuit 3 converts the signal from the sense amplifier into 2-bit data.
The drain of the selected cell and the cell current ICELL of the bit line have four level values and are compared with three reference currents IREF1, IREF2 and IREF3. The cell current ICELL and the reference currents IREF1, IREF2 and IREF3 are compared by the sense amplifier. As a result of the comparison, if the cell current ICELL is larger than the reference currents IREF1, IREF2 and IREF3, the output signal values SA0, SA1 and SA2 from the sense amplifier become "0", respectively.
For example, assume that four current level values of the cell current ICELL are IL1, IL2, IL3 and IL4, and the data D1 and D0 are two bit output data are defined as (0,0), (0,1), (1,0), (1,1). In this case, if the cell current ICELL is identical with the first current level value IL1, the output values SA0, SA1 and SA2 from the sense amplifier all become "0". When coding the value, the output data D1 and D0 all become "0". Multiple threshold voltages and reference currents are shown in FIG. 2.
The current ICELL flowing in the bit line in the sensing mode becomes one of four current level values IL1, IL2, IL3 and IL4. Therefore, in the sensing mode, the current is consumed on the bit line in which the cell current Icel flows and consumed on up to three sensing lines.
As described above, the related out sensing circuit for a multiple level cell has various disadvantages. If the applied word line voltage is large, a high current flows on the bit line so that the consumed current increases. If the window of the threshold voltage programmed by the multiple level cell is wide, the voltage of the word line is higher than the maximum threshold voltage in the sensing mode, and the excess current flows in the cell having a lower threshold voltage.
If the voltage consumption is limited in one chip, the number of cells that are concurrently sensed should be a corresponding predetermined number. In addition, as the number of multiple levels stored in one cell is increased, the number of the sense amplifiers is increased. Therefore, the size of the circuit is increased. Accordingly, since a portable system needs a low power nonvolatile memory, the related art circuit is not applicable to the portable system.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.